A Novel Dedicated Low Power 64 Bit Digital Comparator Using Cmos Logic

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1.2. CMOS Based 64 Bit Digital Comparator

64-bit binary comparator compares two numbers each having 64 bits (A63 to A0 & B63 to B0. This comparator is designed by combining seven numbers of 8 bit comparators and a final decision maker single 4 bit comparator arranged in hierarchical fashion ^[4].

1.3. Circuit Diagram of Cmos Based 8 Bit Comparator

Figure 2. Circuit diagram of 8 bit comparator

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1.4. Circuit Description of 8 Bit Comparator

In this, the magnitude of two binary numbers is compared by identifying the locations of the first 1 from the MSB. The one that has the first 1 in most significant position is the largest. In case that the locations of the first 1 are the same in both numbers, the decision is postponed to the lower bit where only one input has 1 in that bit position if X >Y, Output comp = 1 and if X ≤Y, Output comp =0.

The results less than or equal to are conveyed by the same output Comp. This circuit uses basic logic gates such as NAND gates, NOR gates, inverters and a 2:1 Mux ^[5].

In general the sum of Mux gates in n-bit comparator is given by

The total number of gate count in n-bit comparator is

1.5. CMOS Implementation of 8 Bit Comparator

Figure 3. CMOS implementation of 8 bit comparator

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1.6. Design of 64 Bit Comparator Using Eight 8 Bit Versions and One 4 Bit Version

The proposed design strategy uses a hierarchical design of a full cmos 64-bit comparator is shown in Figure 3.4, which is composed of eight 8-bit comparators and one final 4 bit comparator. The 64 bits are divided into eight bytes which are evaluated at the same time, and then the 4-bit comparator produces the final output signal ^[6].

Figure 4. Circuit diagram of 64bit comparator

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2. Circuit Description

To improve the speed and reduce power consumption, several designs rely on pipelining and power-down mechanisms to reduce switching activity with respect to the actual input operands’ bit values. This design uses all-N-transistor (ANT) circuits to compensate for high fan-in with high line throughput. This circuitry leverage custom logic gates for performing comparison. This architecture splits a 64-b comparator into two comparator stages, the ﬁrst stage consists of eight modules performing 8-b comparisons and the modules’ outputs are input into a second stage. The second stage uses a 4 bit comparator to get the final result ^[7].

This proposed design strategy uses a hierarchical design of a fast 64-bit comparator is shown in Figure 4.3, which is composed of eight 8-bit comparators and one final 4-bit comparator. The 64 bits are divided into eight bytes which are evaluated at the same time, and then the 4-bit comparator produces the final output signal. This modified 64 bit comparator depicts A<B, A=B and A>B respectively ^[8].

3. Simulation Result & Analysis

Figure 5. Experimental result of CMOS based 64 bit comparator for A>B

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Figure 6 Experimental result of CMOS based 64 bit comparator for A≤B

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We have performed simulation of the proposed design by using Tanner EDA tools with 180 nm technology at room temp. i.e. 27C. In this experiment we have adjusted the aspect ratios i.e. (W/L) of both PMOS and NMOS transistors so as to get the accurate results.

The experiment has been performed by considering different values of the two 64 bit numbers.

The design is simulated at different power supply voltage ranging from 1v to 5v and corresponding delay is measured with the target to reach less power delay product (PDP) I.e. energy.

3.1. Power Comparison

The average power consumption is also measured by applying a complete pattern during a long period of time. In this experiment, the Existing and modified comparators are simulated at 180 nm nm feature size by varying supply voltages ranging from 1v to 5v with 1v as step size.

Table 1. Comparision between power supply and power consumed

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Simulation results for 64 bit digital comparator using CMOS style.

Table 2. comparision between power supply and pdp

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Simulation results for 64 bit digital comparator using CMOS style.

3.1.1. Power Supply vs Power Consumed for Cmos

The power consumption for existing designs are calculated by performing simulation of circuit. Simulation results for power consumptions by varying supply voltage ranging from 1v to 5v with 1v as step size is shown as below.

Figure 7. Graph between power supply and power consumed

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3.2. Delay Consideration

The delay is also measured by applying a complete pattern during a long period of time. In this experiment, the comparators are simulated at 180 nm feature size by varying supply voltages ranging from 3v to 5v with 1v as step size.

Figure 8. comparisons between delays of proposed design

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Figure 9. Comparision between power supply and delay

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3.3. Power Delay Product Consideration

The PDP is a qualitative measure of efficiency and compromise between power dissipitation and speed. PDP is particularly important When low power operation is needed. The average power consumption and average delay is calculated to find the energy required for the proper operation of the circuit is calculated and tabulated as below.

Figure 10. Comparision between power supply and pdp

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