Figure 8. comparisons between delays of proposed design

From

A Novel Dedicated Low Power 64 Bit Digital Comparator Using Cmos Logic

Shilparani Panda, Asirbad Behera, Manas Ranjan Jena, Snigdharani Nath

Journal of Embedded Systems. 2014, 2(2), 28-31 doi:10.12691/jes-2-2-2