Figures index

From

A Novel Dedicated Low Power 64 Bit Digital Comparator Using Cmos Logic

Shilparani Panda, Asirbad Behera, Manas Ranjan Jena, Snigdharani Nath

Journal of Embedded Systems. 2014, 2(2), 28-31 doi:10.12691/jes-2-2-2
  • Figure 1. Schematic of hierarchical design
  • Figure 2. Circuit diagram of 8 bit comparator
  • Figure 3. CMOS implementation of 8 bit comparator
  • Figure 4. Circuit diagram of 64bit comparator
  • Figure 5. Experimental result of CMOS based 64 bit comparator for A>B
  • Figure 6 Experimental result of CMOS based 64 bit comparator for A≤B
  • Figure 7. Graph between power supply and power consumed
  • Figure 8. comparisons between delays of proposed design
  • Figure 9. Comparision between power supply and delay
  • Figure 10. Comparision between power supply and pdp