Figure 3.1. Circuit diagram of minority function bridge style full adder

From

Design of an Efficient Dedicated Low Power High Speed Full Adder

Asirbad Behera, Manas Ranjan Jena, Abhinna Das, Narendra Kumar Pattnayak

Journal of Embedded Systems. 2014, 2(3), 35-38 doi:10.12691/jes-2-3-1