Figure 3.2. Synthesis output of ALU

From

Design of an Efficient Low Power 4-bit Arithmatic Logic Unit (ALU) Using VHDL

Giridhari Muduli, Bibhudatt Pradhan, Manas Ranjan Jena, Snigdharani Nath

International Transaction of Electrical and Computer Engineers System. 2014, 2(5), 144-148 doi:10.12691/iteces-2-5-3