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CMOS Voltage-Controlled Negative Resistance Realization

Soumya Mourya, Raj Senani
American Journal of Electrical and Electronic Engineering. 2020, 8(4), 120-124. DOI: 10.12691/ajeee-8-4-4
Received July 30, 2020; Revised September 01, 2020; Accepted September 10, 2020

Abstract

In this communication, a new CMOS circuit configuration is proposed to realize a voltage-controlled negative resistance (VCNR) which has been implemented using only eight MOS transistors- all working in the saturation region. The value of the realized negative resistance is controlled by two identical and opposite external DC voltages. The workability of the proposed circuit has been confirmed by Cadence Virtuoso simulations and some sample results have been given. The proposed VCNR circuit has been shown to exhibit good linearity, has good variable negative resistance range from -1.05kΩ and -300Ω and offers a good operational frequency range up to around 100 MHz with total power dissipation between 0.5mW- 8.73mW only.

1. Introduction

In recent years, electronically-controllable resistors are preferred for integrated circuit (IC) applications and implementations rather than passive resistors fabricated on the IC chips because the latter occupy relatively much larger chip area and have limited accuracy. On the other hand, actively-simulated resistors are extremely suitable because they require considerably reduced chip area and provide electronic-controllability of their values through an external voltage or current. Thus, the voltage-controlled resistances (VCR) are attractive components for many electronically-controllable functional circuits such as voltage-controlled filters, voltage-controlled oscillators (VCO), voltage-controlled phase-shifters, and several others.

Motivated by the above, there have been many studies on the realization of electronically-controllable resistors in the earlier literature, for instance, see 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31. In earlier works, there are some VCR circuits which were devised based upon the use of JFETs 1, 2, 3, 4, 5, 6, 7, 17, 18, 26, 28, 30 while some current-controlled resistances using BJTs have also been proposed such as those in 8, 9. On the other hand, the grounded VCRs proposed in 10, 11, 12, 13, 14, 15, 16, 21, 22, 23, 24 employ MOS transistors operating in triode/saturation regions in which those operating in the former regime exhibit a square nonlinearity in the expression of their drain current which is canceled with an appropriately devised additional MOS-transistors-based circuitry. Many such linearized VCRs or more general linearized voltage-controlled impedances based upon such ideas of nonlinearity-cancellation have also been formulated with the help of a variety of analog building blocks such as operational amplifiers 2, 3, 4, 5, 7, 17, 18, Operational transconductance amplifiers (OTA) 19, second-generation Current Conveyors (CCII) as in 6 (also see 7 and 26), current feedback op-amps (CFOA) along with a JFET/MOSFET and a few resistors, as in 28, 30 and CFOAs and an analog multiplier as in 29. Lastly, it must also be pointed out that a low power VCR has also been devised using an FGMOS transistor in 20.

From the survey of the earlier published literature, it has been revealed that while a large number of circuits//techniques have been advanced for realizing voltage-controlled positive resistances (VCPR), comparatively fewer circuits have been evolved to realize voltage-controlled negative resistances (VCNR). The various previously known VCNR circuits are as follows:

In reference 8, a two-op-amp-FET-based VCNR is presented while references 17, 18 have presented universal voltage controlled impedance (VCZ) configurations employing two and three op-amps respectively, besides a JFET and a few resistors, both of which can be configured either as VCPR or VCNR as special cases. However, these propositions suffer from the drawback of requiring a larger number of total active and passive components. On the other hand, the floating VCNR presented in 25 is based upon CMOS technology using the method of conversion of transconductance to resistance but this circuit employs two op-amps also. Lastly, 27 deals with a floating VCNR as a special case, realizable with two operational mirrored amplifiers (OMA), a JFET and a number of passive resistors. The general configurations of 28, 30 can realize grounded VCNRs using two CFOAs and floating VCNRs using three or more CFOAs along with a single JFET/MOSFET and a few resistors. On the other hand, the three-CFOA-one analog multiplier-based circuits of 29 suffer from the use of an excessive number of active elements besides requiring a few passive resistors as well. In reference 31 a second generation current conveyor (CCII+) is used as a negative impedance convertor (NIC) to design a VCNR.

Recently, Yuce, Minaei, and Alpaslan in 10 presented a grounded VCPR circuit which employs only eight MOSFETs and is, thus, very economical and suitable for implementation in CMOS technology. In fact, this circuit, employing only eight MOSFETs can be considered to be the simplest and most economical circuit for realizing a grounded VCPR evolved so far. However, to the best of the present authors’ knowledge, any equally simple and economical circuit for realizing a VCNR was neither hinted or implied in 10 nor has subsequently been presented in the literature by the same or any other author so far.

The main intention of this communication is, therefore, to present a VCNR configuration which has been derived by an appropriate rearrangement of the basic MOS sub-circuits employed in the grounded VCPR of 10 and therefore, employs only eight MOSFETs like the circuit of 10.

The workability and the performance of the presented VCNR configuration have been demonstrated by the results of the simulations on CADENCE Virtuoso using 180 nm CMOS technology parameters.

2. The Proposed VCNR Configuration

The proposed CMOS circuit is shown in Figure 1 which contains eight MOS transistors all operating in saturation region. The following condition must be followed by the input voltage and DC bias voltages of this VCNR for ensuring the operation of all the MOSFTs in saturation:

(1)

Ignoring the channel length modulation effect, the equations for the drain currents of the various MOS transistors can be written as follows:

(2)
(3)
(4)
(5)

where and are the threshold voltages of NMOS and PMOS transistors respectively. All PMOS transistors Mi, i=1-4, all NMOS transistors Mj, j=5-8 are assumed to be identical, however, the transconductance parameters are assumed to be and Mobility is denoted by the symbol (for NMOS) and (for PMOS), is the oxide capacitance of both the type of MOS transistors and W/L is the aspect ratio of all the MOS transistors which is assumed to be the same.

In the circuit, the two current mirrors (- and ) are used to copy the drain currents of and respectively by assuming that the MOS transistors of both the current mirrors are matched.

The input node equation can now be written as:

(6)

By solving equations (2)-(6), the input resistance of the circuit, with kp= kn= k for all MOSFETs, is found to be:

(7)

Thus, the circuit realizes a VCNR whose value is controllable through subject to the satisfaction of the conditions dictated by (1).

It may be noted that the DC voltages and are both DC bias supply voltages and as well as the controlling voltages which may be used to vary the value of the negative resistance realized. Thus, it may be noted that, in contrast to the circuit of 10 which employs two dual DC power supplies, we use only a single dual supply.

3. Simulation Results

The simulation of the VCNR of Figure 1 was carried out on CADENCE at gpdk 180nm technology. The sizing of the MOS transistors was done such that every PMOS had W/L ratio of 23.75μm/1μm and W/L ratio of all the NMOS was 7.5μm/1μm. Figure 2 shows the I-V characteristic for different values of the control voltage Applying a DC current at the input and sweeping the same, the DC analysis was performed. The good linearity of the realized negative resistance and its variability with control voltage is established from the plots of Figure 2.

Figure 3 shows the variation of Req with the controlling voltage The value of negative resistance has been found to vary between -1.05kΩ to -300Ω.

To determine the operational frequency range of the proposed VCNR circuit, the magnitude of Req at different frequencies was determined which is shown in Figure 4. The bandwidth of the circuit when realizing different values of Req at different values of the control voltages are found to be around 100 MHz.

The graph of power dissipation with applied control voltage is shown in Figure 5. The maximum power dissipation was found to be 8.73mW while the minimum was of the order of 0.5mW.

The overall performance of the proposed VCNR was, thus, found to be quite satisfactory.

  • Table 1. Comparative Analysis of Earlier VCNRs Available in Literature Designed Without any Active Building Blocks

  • View option

4. Comparison with Previously Known VCNR Circuits and Concluding Remarks

Compared to the previously known VCNR circuits which employ various analog building blocks such as op-amps as in 3, 17, 18, OMAs as in 27, and CFOAs as in 28, 30 all of which would require a large number of MOSFETs when these would be implemented in CMOS technology (for instance, see 4), the proposed VCNR requires a very small number of (only eight) MOSFTs (like the VCPR circuit of 10) and is, therefore, highly suitable for implementation in CMOS technology.

On the other hand, a comparison of the proposed circuit with only transistor-level VCNRs (i.e. which do not require any additional active building blocks), such as those of 8, 20, 25, is shown in Table 1 from where it is revealed that performance-wise, the proposed VCNR circuit of Figure 1 exhibited good linearity, has good variable negative resistance range variable from -1.05kΩ to -300Ω and offers a good operational frequency range up to around 100 MHz with total power dissipation remaining between 0.5mW- 8.73mW while employing a very small number of (only 8 ) MOSFET.

It is expected that the proposed VCNR may find applications in realizing voltage-controlled attenuator/ amplifier, design of variable-bandwidth band-pass filters or Q-enhancement circuits.

In view of the requirement of floating voltage-controlled-resistance circuits in several applications, a worthwhile problem is to find a floating version of the proposed grounded VCNR circuit. This, however, is left for future work.

References

[1]  Von Ow H. P, “Reducing distortion in controlled attenuators using FET,” Proceedings of the IEEE, 56(10), 1718-1719. 1968.
In article      View Article
 
[2]  Nay K. W., and Budak A., “A voltage-controlled resistance with wide dynamic range and low distortion,” IEEE Transactions on Circuits and Systems, 30(10), 770-772. 1983.
In article      View Article
 
[3]  Nay K., and Budak A., “A variable negative resistance,” IEEE Transactions on Circuits and Systems, 32(11), 1193-1194. 1985.
In article      View Article
 
[4]  Senani R., Bhaskar D. R., Gupta S. S., and Singh V. K., “A configuration for realizing floating, linear, voltage‐controlled resistance, inductance and FDNC elements,” International Journal of Circuit Theory and Applications, 37(5), 709-719. 2009.
In article      View Article
 
[5]  Senani R., and Bhaskar D. R., “A simple configuration for realizing voltage-controlled impedances,” IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications, 39(1), 52-59. 1992.
In article      View Article
 
[6]  Maundy Brent, S. Gift, and P. Aronhime. “Practical voltage/current-controlled grounded resistor with dynamic range extension.” IET circuits, devices and systems 2.2 (2008): 201-206. 2008.
In article      View Article
 
[7]  Senani R., and Bhaskar D. R., “Comment: Practical voltage/current-controlled grounded resistor with dynamic range extension.” IET Circuits, Devices and Systems 2.5 (2008): 465-466. 2008.
In article      View Article
 
[8]  Pawarangkoon P., Intaudom V., and Kiranon W., “Electronically tunable floating resistor,” 2004 IEEE Region 10 Conference TENCON 2004, Vol. 500, pp. 372-375. 2004.
In article      
 
[9]  Senani R., Singh A. K., and Singh V. K., “A new floating current-controlled positive resistance using mixed translinear cells,” IEEE Transactions on Circuits and Systems II: Express Briefs, 51(7), 374-377. 2004.
In article      View Article
 
[10]  Yuce E., Minaei S., and Alpaslan H., “Novel CMOS technology-based linear grounded voltage controlled resistor,” Journal of Circuits, Systems, and Computers, 20(03), 447-455. 2011.
In article      View Article
 
[11]  Wang Z., “Novel voltage-controlled grounded resistor,” Electronics Letters, 26(20), 1711-1712. 1990.
In article      View Article
 
[12]  Wilson G., and Chan P. K., “Novel voltage-controlled grounded resistor,” Electronics Letters, 25(25), 1725-1726. 1989.
In article      View Article
 
[13]  Moon G., Zaghloul M. E., and Newcomb R. W., “An enhancement-mode MOS voltage-controlled linear resistor with large dynamic range,” IEEE Transactions on Circuits and Systems, 37(10), 1284-1288. 1990.
In article      View Article
 
[14]  Al-Ruwaihi K. M., and Noras J. M., “A novel linear resistor utilizing MOS transistors with identical sizes and one controlling voltage,” International Journal of Electronics, 76(6), 1083-1098. 1994.
In article      View Article
 
[15]  Yuce E., Shahram Minaei, and Norbert Herencsar, “Grounded voltage controlled positive resistor with ultra-low power consumption,” Elektronika Ir Elektrotechnika 20.7, 45-50. 2014.
In article      View Article
 
[16]  Yüce E., Minaei S., Alpaslan H. “Single voltage controlled CMOS grounded resistors and their application to video filter,” Indian Journal of Engineering and Materials Sciences, 21(5), 501- 509. 2014.
In article      
 
[17]  Senani, R., “Universal linear voltage-controlled-impedance configuration,” IEE Proceedings-Circuits,Devicesand Systems, 142(3), 208-208. 1995.
In article      View Article
 
[18]  Senani R., and Bhaskar D. R., “Versatile voltage-controlled impedance configuration,” IEE Proceedings-Circuits, Devices and Systems, 141(5), 414-416. 1994.
In article      View Article
 
[19]  Kaewdang K., Kumwachara K., and Surakampontorn W., “Electronically tunable floating CMOS resistor using OTA,” In IEEE International Symposium on Communications and Information Technology, 2005. ISCIT 2005. (Vol. 1, pp. 729-732). 2005.
In article      
 
[20]  Pandey R., and Gupta M., “FGMOS based voltage-controlled grounded resistor and its applications,” Radioengineering, 19(3), 455-459. 2010.
In article      
 
[21]  Elwan H. O., Mahmoud S. A., and Soliman A. M., “CMOS voltage controlled floating resistor,” International Journal of Electronics, 81(5), 571-576. 1996.
In article      View Article
 
[22]  Nagaraj K., “New CMOS floating voltage-controlled resistor,” Electronics Letters, 22(12), 667-668. 1986.
In article      View Article
 
[23]  Mahmoud S. A., Elwan H. O., and Soliman A. M., “CMOS voltage controlled floating resistors,” Microelectronics Journal, 28, 627-640. 1997.
In article      View Article
 
[24]  Banu M., and Tsividis Y., “Floating voltage-controlled resistors in CMOS technology,” Electronics Letters, 18(15), 678-679. 1982.
In article      View Article
 
[25]  Tadic N., and Gobovic D., “A floating, negative-resistance voltage-controlled resistor,” Proceedings of the 18th IEEE Instrumentation and Measurement Technology Conference. Rediscovering Measurement in the Age of Informatics (Cat. No. 01CH 37188) (Vol. 1, pp. 437-442). 2001.
In article      
 
[26]  Maundy B., Gift S., and Aronhime P. (2008). Reply to: Practical voltage/current controlled grounded resistor with dynamic range extension. IET Circuits, Devices and Systems, 5(2), 467. 2008.
In article      View Article
 
[27]  Senani R. “Floating GNII/GNIC configuration realized with a single OMA”, Electronics Letters, 31(6), pp. 423-425, 1995.
In article      View Article
 
[28]  Senani R, “Realization of a class of analog signal processing/signal generation Circuits: novel applications of Current feedback operational amplifiers”, Frequenz: Journal of Telecommunications, 1998.
In article      View Article
 
[29]  Senani R., Bhaskar D.R., Tripathi M.P. and Jain M.K. (2016) Canonic Realizations of Voltage-Controlled Floating Inductors Using CFOAs and Analog Multipliers. Circuits and Systems, 7, 3617-3625.
In article      View Article
 
[30]  Senani R., Bhaskar D. R., Singh A. K. and Singh V. K., Current feedback operational amplifiers and Their Applications, Springer, New-York, USA, 2013, chapter-3, 49-80.
In article      
 
[31]  Popovic Jelena, and Aleksandra Pavasovic. “Voltage-driven negative impedance converter based on the modified Fabre-Normand CMOS current conveyor.” 24th international conference on microelectronics (IEEE Cat. No. 04TH8716). Vol. 2. IEEE, 2004.
In article      
 

Published with license by Science and Education Publishing, Copyright © 2020 Soumya Mourya and Raj Senani

Creative CommonsThis work is licensed under a Creative Commons Attribution 4.0 International License. To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/

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Soumya Mourya, Raj Senani. CMOS Voltage-Controlled Negative Resistance Realization. American Journal of Electrical and Electronic Engineering. Vol. 8, No. 4, 2020, pp 120-124. http://pubs.sciepub.com/ajeee/8/4/4
MLA Style
Mourya, Soumya, and Raj Senani. "CMOS Voltage-Controlled Negative Resistance Realization." American Journal of Electrical and Electronic Engineering 8.4 (2020): 120-124.
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Mourya, S. , & Senani, R. (2020). CMOS Voltage-Controlled Negative Resistance Realization. American Journal of Electrical and Electronic Engineering, 8(4), 120-124.
Chicago Style
Mourya, Soumya, and Raj Senani. "CMOS Voltage-Controlled Negative Resistance Realization." American Journal of Electrical and Electronic Engineering 8, no. 4 (2020): 120-124.
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  • Table 1. Comparative Analysis of Earlier VCNRs Available in Literature Designed Without any Active Building Blocks
[1]  Von Ow H. P, “Reducing distortion in controlled attenuators using FET,” Proceedings of the IEEE, 56(10), 1718-1719. 1968.
In article      View Article
 
[2]  Nay K. W., and Budak A., “A voltage-controlled resistance with wide dynamic range and low distortion,” IEEE Transactions on Circuits and Systems, 30(10), 770-772. 1983.
In article      View Article
 
[3]  Nay K., and Budak A., “A variable negative resistance,” IEEE Transactions on Circuits and Systems, 32(11), 1193-1194. 1985.
In article      View Article
 
[4]  Senani R., Bhaskar D. R., Gupta S. S., and Singh V. K., “A configuration for realizing floating, linear, voltage‐controlled resistance, inductance and FDNC elements,” International Journal of Circuit Theory and Applications, 37(5), 709-719. 2009.
In article      View Article
 
[5]  Senani R., and Bhaskar D. R., “A simple configuration for realizing voltage-controlled impedances,” IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications, 39(1), 52-59. 1992.
In article      View Article
 
[6]  Maundy Brent, S. Gift, and P. Aronhime. “Practical voltage/current-controlled grounded resistor with dynamic range extension.” IET circuits, devices and systems 2.2 (2008): 201-206. 2008.
In article      View Article
 
[7]  Senani R., and Bhaskar D. R., “Comment: Practical voltage/current-controlled grounded resistor with dynamic range extension.” IET Circuits, Devices and Systems 2.5 (2008): 465-466. 2008.
In article      View Article
 
[8]  Pawarangkoon P., Intaudom V., and Kiranon W., “Electronically tunable floating resistor,” 2004 IEEE Region 10 Conference TENCON 2004, Vol. 500, pp. 372-375. 2004.
In article      
 
[9]  Senani R., Singh A. K., and Singh V. K., “A new floating current-controlled positive resistance using mixed translinear cells,” IEEE Transactions on Circuits and Systems II: Express Briefs, 51(7), 374-377. 2004.
In article      View Article
 
[10]  Yuce E., Minaei S., and Alpaslan H., “Novel CMOS technology-based linear grounded voltage controlled resistor,” Journal of Circuits, Systems, and Computers, 20(03), 447-455. 2011.
In article      View Article
 
[11]  Wang Z., “Novel voltage-controlled grounded resistor,” Electronics Letters, 26(20), 1711-1712. 1990.
In article      View Article
 
[12]  Wilson G., and Chan P. K., “Novel voltage-controlled grounded resistor,” Electronics Letters, 25(25), 1725-1726. 1989.
In article      View Article
 
[13]  Moon G., Zaghloul M. E., and Newcomb R. W., “An enhancement-mode MOS voltage-controlled linear resistor with large dynamic range,” IEEE Transactions on Circuits and Systems, 37(10), 1284-1288. 1990.
In article      View Article
 
[14]  Al-Ruwaihi K. M., and Noras J. M., “A novel linear resistor utilizing MOS transistors with identical sizes and one controlling voltage,” International Journal of Electronics, 76(6), 1083-1098. 1994.
In article      View Article
 
[15]  Yuce E., Shahram Minaei, and Norbert Herencsar, “Grounded voltage controlled positive resistor with ultra-low power consumption,” Elektronika Ir Elektrotechnika 20.7, 45-50. 2014.
In article      View Article
 
[16]  Yüce E., Minaei S., Alpaslan H. “Single voltage controlled CMOS grounded resistors and their application to video filter,” Indian Journal of Engineering and Materials Sciences, 21(5), 501- 509. 2014.
In article      
 
[17]  Senani, R., “Universal linear voltage-controlled-impedance configuration,” IEE Proceedings-Circuits,Devicesand Systems, 142(3), 208-208. 1995.
In article      View Article
 
[18]  Senani R., and Bhaskar D. R., “Versatile voltage-controlled impedance configuration,” IEE Proceedings-Circuits, Devices and Systems, 141(5), 414-416. 1994.
In article      View Article
 
[19]  Kaewdang K., Kumwachara K., and Surakampontorn W., “Electronically tunable floating CMOS resistor using OTA,” In IEEE International Symposium on Communications and Information Technology, 2005. ISCIT 2005. (Vol. 1, pp. 729-732). 2005.
In article      
 
[20]  Pandey R., and Gupta M., “FGMOS based voltage-controlled grounded resistor and its applications,” Radioengineering, 19(3), 455-459. 2010.
In article      
 
[21]  Elwan H. O., Mahmoud S. A., and Soliman A. M., “CMOS voltage controlled floating resistor,” International Journal of Electronics, 81(5), 571-576. 1996.
In article      View Article
 
[22]  Nagaraj K., “New CMOS floating voltage-controlled resistor,” Electronics Letters, 22(12), 667-668. 1986.
In article      View Article
 
[23]  Mahmoud S. A., Elwan H. O., and Soliman A. M., “CMOS voltage controlled floating resistors,” Microelectronics Journal, 28, 627-640. 1997.
In article      View Article
 
[24]  Banu M., and Tsividis Y., “Floating voltage-controlled resistors in CMOS technology,” Electronics Letters, 18(15), 678-679. 1982.
In article      View Article
 
[25]  Tadic N., and Gobovic D., “A floating, negative-resistance voltage-controlled resistor,” Proceedings of the 18th IEEE Instrumentation and Measurement Technology Conference. Rediscovering Measurement in the Age of Informatics (Cat. No. 01CH 37188) (Vol. 1, pp. 437-442). 2001.
In article      
 
[26]  Maundy B., Gift S., and Aronhime P. (2008). Reply to: Practical voltage/current controlled grounded resistor with dynamic range extension. IET Circuits, Devices and Systems, 5(2), 467. 2008.
In article      View Article
 
[27]  Senani R. “Floating GNII/GNIC configuration realized with a single OMA”, Electronics Letters, 31(6), pp. 423-425, 1995.
In article      View Article
 
[28]  Senani R, “Realization of a class of analog signal processing/signal generation Circuits: novel applications of Current feedback operational amplifiers”, Frequenz: Journal of Telecommunications, 1998.
In article      View Article
 
[29]  Senani R., Bhaskar D.R., Tripathi M.P. and Jain M.K. (2016) Canonic Realizations of Voltage-Controlled Floating Inductors Using CFOAs and Analog Multipliers. Circuits and Systems, 7, 3617-3625.
In article      View Article
 
[30]  Senani R., Bhaskar D. R., Singh A. K. and Singh V. K., Current feedback operational amplifiers and Their Applications, Springer, New-York, USA, 2013, chapter-3, 49-80.
In article      
 
[31]  Popovic Jelena, and Aleksandra Pavasovic. “Voltage-driven negative impedance converter based on the modified Fabre-Normand CMOS current conveyor.” 24th international conference on microelectronics (IEEE Cat. No. 04TH8716). Vol. 2. IEEE, 2004.
In article