DVCC Based K.H.N. Biquadratic Analog Filter with Digitally Controlled Variations

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2. DVCC

DVCC is a five-terminal active analog building block illustrated in Figure 1, with terminal characteristics described by the following matrix equation ^[15].

(1)

DVCC exhibits negligible (ideally zero) input resistance at terminal X, and very high (ideally infinite) resistance at both Y terminals as well as the Z terminal. The output current follows the input current direction with both currents flowing either into or out of the device. The CMOS implementation of DVCC is as shown in Figure 2.

Figure 2. CMOS realization of the dual-output DVCC [15]

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IMPLEMENTATION OF KHN BIQUAD

The implemented KHN biquad is illustrated in Figure 3. The analysis of the circuit yields the following equations (2), (3) and (4).

Figure 3. K.H.N. Biquad Filter Realization [14]

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(2)

(3)

(4)

The resonant angular frequency ⍵_o, and the quality factor, Q, are given by (5) and (6) respectively.

(5)

(6)

We can see that lowpass, bandpass and highpass functions can be simultaneously realized without changing the topology.

In simulations, using PSPICE the DVCC was realized by the CMOS implementation shown in Figure 2 using TSMC 0.25-µm process parameters. The aspect ratios of the CMOS transistors of the DVCC are presented in Table I. The supply voltages were taken as, V_DD =−V_SS = 2 V and the biasing voltages were assigned values, V_B1 =−1.32 V and V_B2 = +0.7 V. The circuit was designed for f_o = ω_o/2π = 100 kHz and Q = 0.707 by choosing R₁ = R₂ =R₃= R₄= 1 kΩ and C₂ =2 C₁ = 1.125 nF. The responses of the multifunctional filter are shown in Figure 4 (a) and Figure 4 (b). The results are in full conformity with the theoretical analysis.

Figure 4 (a). Simulated Lowpass and Highpass responses

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Figure 4 (b). Simulated Bandpass response

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Table 1. Aspect ratios of the cmos transistors of the dvcc [15]

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3. DC-DVCC

To introduce the programmability in the multifunctional filter we have used a digitally controlled DVCC (DC-DVCC) shown in Figure 5. The modified terminal characteristics for the same are as follows

(7)

Where:

(8)

For obtaining the digital control in the DVCC current summing networks (CSNs) are employed at the Z (Z+ and Z-) terminals for controlling the current transfer gain parameter k. The gain parameter k shows a variation from 1 to (2ⁿ – 1), where n is the number of transistor arrays. The modified circuit of DVCC with the transistors arrays is as shown in Figure 5. The CSN consists of n transistor pairs, the aspect ratios of whose PMOS and NMOS transistors respectively are given by:

(9)

(10)

Furthermore, the current at the Z terminal which is assumed to be flowing out of the DC-DVCC, can be expressed by:

(11)

Therefore, the proposed DC-DVCC provides a current transfer gain, k equal to:

(12)

Where d_i are the bits applied to the i-th branch in the CSN. Now the current flow in a particular branch is enabled or disabled depending upon whether d_i is a logic 1 or logic 0 ^[16].

4. Comparative Study of Variation in Bandpass Filter Resonant Frequency

In this section the discussion is restricted to the variation in resonant frequency of Band Pass filter only. The circuit shown in Figure 3 was modified by replacing a DVCC block with a DC-DVCC block, one by one so that change in relationship between the resonant frequency and control word can be observed. Each block is assigned an individual gain α, β and γ respectively. The analysis is done and the following expression was obtained for the band pass response.

(13)

The resonant frequency is now defined as

(14)

As could be clearly seen from (14) the resonant frequency of the Bandpass filter can be controlled by changing the values of the gain parameters α, β and γ. This variation will not require any change in the values of the passive components.

In the analysis that follows it is assumed that if the DVCC is replaced by DC-DVCC the gain parameter for respective block takes the value k, however if the DVCC is retained, the gain parameter attains value equal to 1.

Figure 5. CMOS realization of the DC- DVCC having gain k

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Replacing the first block (corresponding to α) by DC-DVCC, therefore for this configuration we have α= k and β=γ= 1, hence the equation for the band-pass response and the expression for the resonant frequency are respectively given by:

(15)

(16)

The configuration is illustrated in Figure 6.

Figure 6. Configuration for α= k and β=γ= 1

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From (16) it is evident that the resonant frequency varies with the control word k, in a square root fashion. The configuration shown in Figure 6 is simulated using PSPICE and the Bandpass reses obtained for the control word ([0 0 1] and [1 1 1]) are shown in Figure 7 (a) and Figure 7 (b).

Figure 7(a). Simulated magnitude response (in dB) for band pass filter with control word [d₂d₁ d₀ = 0 0 1] selected for circuit of Figure 6

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Figure 7(b). Simulated magnitude response (in dB) for band pass filter with control word [d₂d₁ d₀ = 1 1 1] selected for circuit of Figure 6.

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The simulations show a gradual increase in the resonant frequency when the control word is increased, the observations are recorded in Table II.

Now when the second block is replaced the value of the gain parameters changes to α= β=k and γ= 1 hence the equation for the band-pass response and the expression for the resonant frequency are respectively given by:

(17)

(18)

The configuration is illustrated in Figure 8

Figure 8. Configuration for α= k and β=γ= k

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From (18) it is evident that the resonant frequency varies with the control word k, in a linear fashion. The configuration shown in Figure 8 is simulated using PSPICE and the Bandpass reses obtained for the control word ([0 0 1] and [1 1 1]) are shown in Figure 9 (a) and Figure 9 (b).

Figure 9(a). Simulated magnitude response (in dB) for band pass filter with control word [d₂d₁ d₀ = 0 0 1] selected for circuit of Figure 8

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Figure 9(b). Simulated magnitude response (in dB) for band pass filter with control word [d₂d₁ d₀ = 11 1] selected for circuit of Figure 6

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The simulations show an increase in the resonant frequency when the control word is increased, the observations are recorded in Table 2.

When the third block is replaced the value of the gain parameters changes to α= β=γ=k hence the equation for the band-pass response and the expression for the resonant frequency are respectively given by:

(19)

(20)

The configuration is illustrated in Figure 10

Figure 10. Configuration for α= β=γ= k

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From (20) it is evident that the resonant frequency varies with the control word k, in a k^3/2fashion. The configuration shown in Figure 10 is simulated using PSPICE and the Bandpass reses obtained for the control word ([0 0 1] and [1 1 1]) are shown in Figure 11 (a) and Figure 11 (b).

Figure 11(a). Simulated magnitude response (in dB) for band pass filter with control word [d₂d₁ d₀ = 0 0 1] selected for circuit of Figure 10

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Figure 11(b). Simulated magnitude response (in dB) for band pass filter with control word [d₂d₁ d₀ = 1 1 0] selected for circuit of Figure 10

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The simulations show an increase in the resonant frequency when the control word is increased, the observations are recorded in Table 2.

The circuit presented in ^[14] for a particular design worked only for a single frequency but using the modification suggested in this paper the utility of the circuit is increased.

Now the circuit when selected for a particular variation and designed for a particular set of values of resistances and capacitances can work for seven different frequencies.

Table 2. Variation in resonant frequency of bandpass responses with the control word

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Figure 12, Figure 13 and Figure 14 are the plots showing variation in resonant frequency of the Bandpass filter configurations shown in Figure 6, Figure 8, Figure 10.

Figure 12. Variation in resonant frequency of BPF with digital control word for circuit of Figure 6

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Figure 13. Variation in resonant frequency of BPF with digital control word for circuit of Figure 8

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Figure 14. Variation in resonant frequency of BPF with digital control word for circuit of Figure 10

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