Metrics

From
Review of Leakage Power Reduction in CMOS Circuits by Khushboo Kumari, Arun Agarwal, Jayvrat and Kabita Agarwal American Journal of Electrical and Electronic Engineering. 2014, 2(4), 133-136 doi:10.12691/ajeee-2-4-2
Views
23206
Html 22263
Abstract 943
30 August 2014 (publication date) through 18 January 2022 *
15.66 % of article views led to PDF downloads *
*Although we update our data on a daily basis, there may be a 48-hour delay before the most recent numbers are available.
Downloads: 12806
PDF3633
Epub1375
XML1659
PPT2317
Figures3564
Tables258
Export: 3941
RIS1089
BibTex1559
Endnote1293
RIS, BibTex, EndNote allows users to search, retrieve and store citations from bibliographic databases such as ABI Inform, the Web of Science, Anthropological Literature, the MLA bibliography, or the catalogs of individual libraries.
Area Chart Example: If your want to see the details of daily statistics for this article, please click here to login our Manuscript Tracking System.
Citations
5
Found additional citations for the article? Please contact us at submission@sciepub.com.
Shares & bookmarks
Facebook0
Twitter0
LinkedIn0
Google +0
Found additional shares or bookmarks for the article? Please contact us at submission@sciepub.com