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Fig
ure 2.
Stack mode approach using 2 input NOR gate [22]
From
Review of Leakage Power Reduction in CMOS Circuits
Khushboo Kumari, Arun Agarwal, Jayvrat, Kabita Agarwal
American Journal of Electrical and Electronic Engineering
.
2014
, 2(4), 133-136 doi:10.12691/ajeee-2-4-2
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